\chapter{Preface}

This document describes the RISC-V privileged architecture.
This release, version \privrev, contains the following versions of the RISC-V
ISA modules:

{
\begin{table}[hbt]
  \centering
  \begin{tabular}{|c|l|c|}
    \hline
    Module                & Version  & Status\\
    \hline
    \em Machine ISA       & \em 1.13 & \em Draft \\
    \bf Supervisor ISA    & \bf 1.12 & \bf Ratified \\
    \bf Svnapot Extension & \bf 1.0  & \bf Ratified \\
    \bf Svpbmt Extension  & \bf 1.0  & \bf Ratified \\
    \bf Svinval Extension & \bf 1.0  & \bf Ratified \\
    \bf Hypervisor ISA    & \bf 1.0  & \bf Ratified \\
    \hline
  \end{tabular}
\end{table}
}

The following compatible changes have been made to the Machine ISA since version 1.12:
\vspace{-0.2in}
\begin{itemize}
  \parskip 0pt
  \itemsep 1pt
\item Defined the {\tt misa}.V field to reflect that the V extension has been implemented.
\end{itemize}

\section*{Preface to Version 20211203}

This document describes the RISC-V privileged architecture.
This release, version 20211203, contains the following versions of the RISC-V
ISA modules:

{
\begin{table}[hbt]
  \centering
  \begin{tabular}{|c|l|c|}
    \hline
    Module                & Version  & Status\\
    \hline
    \bf Machine ISA       & \bf 1.12 & \bf Ratified \\
    \bf Supervisor ISA    & \bf 1.12 & \bf Ratified \\
    \bf Svnapot Extension & \bf 1.0  & \bf Ratified \\
    \bf Svpbmt Extension  & \bf 1.0  & \bf Ratified \\
    \bf Svinval Extension & \bf 1.0  & \bf Ratified \\
    \bf Hypervisor ISA    & \bf 1.0  & \bf Ratified \\
    \hline
  \end{tabular}
\end{table}
}

The following changes have been made since version 1.11, which, while not
strictly backwards compatible, are not anticipated to cause software
portability problems in practice:
\vspace{-0.2in}
\begin{itemize}
  \parskip 0pt
  \itemsep 1pt
\item Changed MRET and SRET to clear {\tt mstatus}.MPRV when leaving M-mode.
\item Reserved additional {\tt satp} patterns for future use.
\item Stated that the {\tt scause} Exception Code field must implement
  bits 4--0 at minimum.
\item Relaxed I/O regions have been specified to follow RVWMO.  The previous
  specification implied that PPO rules other than fences and acquire/release
  annotations did not apply.
\item Constrained the LR/SC reservation set size and shape when using
  page-based virtual memory.
\item PMP changes require an SFENCE.VMA on any hart that implements
  page-based virtual memory, even if VM is not currently enabled.
\item Allowed for speculative updates of page table entry A bits.
\item Clarify that if the address-translation algorithm non-speculatively
  reaches a PTE in which a bit reserved for future standard use is set,
  a page-fault exception must be raised.
\end{itemize}

Additionally, the following compatible changes have been made since version
1.11:
\vspace{-0.2in}
\begin{itemize}
  \parskip 0pt
  \itemsep 1pt
\item Removed the N extension.
\item Defined the mandatory RV32-only CSR {\tt mstatush}, which contains
  most of the same fields as the upper 32 bits of RV64's {\tt mstatus}.
\item Defined the mandatory CSR {\tt mconfigptr}, which if nonzero
  contains the address of a configuration data structure.
\item Defined optional {\tt mseccfg} and {\tt mseccfgh} CSRs, which control
 the machine's security configuration.
\item Defined {\tt menvcfg}, {\tt henvcfg}, and {\tt senvcfg} CSRs
  (and RV32-only {\tt menvcfgh} and {\tt henvcfgh} CSRs),
  which control various characteristics of the execution environment.
\item Designated part of SYSTEM major opcode for custom use.
\item Permitted the unconditional delegation of less-privileged interrupts.
\item Added optional big-endian and bi-endian support.
\item Made priority of load/store/AMO address-misaligned exceptions
  implementation-defined relative to load/store/AMO page-fault
  and access-fault exceptions.
\item PMP reset values are now platform-defined.
\item An additional 48 optional PMP registers have been defined.
\item Slightly relaxed the atomicity requirement for A and D bit updates
  performed by the implementation.
\item Clarify the architectural behavior of address-translation caches
\item Added Sv57 and Sv57x4 address translation modes.
\item Software breakpoint exceptions are permitted to write either 0
  or the PC to {\em x}\/{\tt tval}.
\item Clarified that bare S-mode need not support the SFENCE.VMA instruction.
\item Specified relaxed constraints for implicit reads of non-idempotent
  regions.
\item Added the Svnapot Standard Extension, along with the N bit in
  Sv39, Sv48, and Sv57 PTEs.
\item Added the Svpbmt Standard Extension, along with the PBMT bits in
  Sv39, Sv48, and Sv57 PTEs.
\item Added the Svinval Standard Extension and associated instructions.
\end{itemize}

Finally, the hypervisor architecture proposal has been extensively revised.

\newpage

\section*{Preface to Version 1.11}

This is version 1.11 of the RISC-V privileged architecture.
The document contains the following versions of the RISC-V ISA
modules:

{
\begin{table}[hbt]
  \centering
  \begin{tabular}{|c|l|c|}
    \hline
    Module             & Version  & Status\\
    \hline
    \bf Machine ISA    & \bf 1.11 & \bf Ratified \\
    \bf Supervisor ISA & \bf 1.11 & \bf Ratified \\
    \em Hypervisor ISA & \em 0.3  & \em Draft \\
    \hline
  \end{tabular}
\end{table}
}

Changes from version 1.10 include:
\vspace{-0.2in}
\begin{itemize}
  \parskip 0pt
  \itemsep 1pt
  \item Moved Machine and Supervisor spec to {\bf Ratified} status.
\item Improvements to the description and commentary.
\item Added a draft proposal for a hypervisor extension.
\item Specified which interrupt sources are reserved for standard use.
\item Allocated some synchronous exception causes for custom use.
\item Specified the priority ordering of synchronous exceptions.
\item Added specification that xRET instructions may, but are not
  required to, clear LR reservations if A extension present.
\item The virtual-memory system no longer permits supervisor mode to execute
  instructions from user pages, regardless of the SUM setting.
\item Clarified that ASIDs are private to a hart, and added commentary about
  the possibility of a future global-ASID extension.
\item SFENCE.VMA semantics have been clarified.
\item Made the {\tt mstatus}.MPP field \warl, rather than \wlrl.
\item Made the unused {\em x}{\tt ip} fields \wpri, rather than \wiri.
\item Made the unused {\tt misa} fields \warl, rather than \wiri.
\item Made the unused {\tt pmpaddr} and {\tt pmpcfg} fields \warl, rather than \wiri.
\item Required all harts in a system to employ the same PTE-update scheme as each other.
\item Rectified an editing error that misdescribed the mechanism by which
  {\tt mstatus}.{\em x}IE is written upon an exception.
\item Described scheme for emulating misaligned AMOs.
\item Specified the behavior of the {\tt misa} and {\em x}{\tt epc} registers in
  systems with variable IALIGN.
\item Specified the behavior of writing self-contradictory values to the
  {\tt misa} register.
\item Defined the {\tt mcountinhibit} CSR, which stops performance
  counters from incrementing to reduce energy consumption.
\item Specified semantics for PMP regions coarser than four bytes.
\item Specified contents of CSRs across XLEN modification.
\item Moved PLIC chapter into its own document.
\end{itemize}

\newpage

\section*{Preface to Version 1.10}

This is version 1.10 of the RISC-V privileged
architecture proposal.  Changes from version 1.9.1 include:

\begin{itemize}
  \parskip 0pt
  \itemsep 1pt
\item The previous version of this document was released under a
  Creative Commons Attribution 4.0 International License by the
  original authors, and this and future versions of this document will
  be released under the same license.
\item The explicit convention on shadow CSR addresses has been removed
  to reclaim CSR space.  Shadow CSRs can still be added as needed.
\item The {\tt mvendorid} register now contains the JEDEC code of the
  core provider as opposed to a code supplied by the Foundation.  This
  avoids redundancy and offloads work from the Foundation.
\item The interrupt-enable stack discipline has been simplified.
\item An optional mechanism to change the base ISA used by supervisor
  and user modes has been added to the {\tt mstatus} CSR, and the
  field previously called Base in {\tt misa} has been renamed to {\tt
    MXL} for consistency.
\item Clarified expected use of XS to summarize additional extension
  state status fields in {\tt mstatus}.
\item Optional vectored interrupt support has been added to the
  {\tt mtvec} and {\tt stvec} CSRs.
\item The SEIP and UEIP bits in the {\tt mip} CSR have been redefined
  to support software injection of external interrupts.
  \item The {\tt mbadaddr} register has been subsumed by a more
    general {\tt mtval} register that can now capture bad
    instruction bits on an illegal instruction fault to speed
    instruction emulation.
\item The machine-mode base-and-bounds translation and protection
  schemes have been removed from the specification as part of moving
  the virtual memory configuration to {\tt sptbr} (now {\tt satp}).  Some of the
  motivation for the base and bound schemes are now covered by the PMP
  registers, but space remains available in {\tt mstatus} to add these
  back at a later date if deemed useful.
\item In systems with only M-mode, or with both M-mode and U-mode but
  without U-mode trap support, the {\tt medeleg} and {\tt mideleg}
    registers now do not exist, whereas previously they returned zero.
\item Virtual-memory page faults now have {\tt mcause} values distinct from
  physical-memory access faults.  Page-fault exceptions can now be
  delegated to S-mode without delegating exceptions generated by PMA
  and PMP checks.
\item An optional physical-memory protection (PMP) scheme has been proposed.
\item The supervisor virtual memory configuration has been moved from the
  {\tt mstatus} register to the {\tt sptbr} register.  Accordingly, the
  {\tt sptbr} register has been renamed to {\tt satp} (Supervisor Address
  Translation and Protection) to reflect its broadened role.
\item The SFENCE.VM instruction has been removed in favor of the improved
  SFENCE.VMA instruction.
\item The {\tt mstatus} bit MXR has been exposed to S-mode via {\tt sstatus}.
\item The polarity of the PUM bit in {\tt sstatus} has been inverted to
  shorten code sequences involving MXR.  The bit has been renamed to SUM.
\item Hardware management of page-table entry Accessed and Dirty bits has
  been made optional; simpler implementations may trap to software to
  set them.
\item The counter-enable scheme has changed, so that S-mode can
  control availability of counters to U-mode.
\item H-mode has been removed, as we are focusing on recursive
  virtualization support in S-mode.  The encoding space has been
  reserved and may be repurposed at a later date.
\item A mechanism to improve virtualization performance by
  trapping S-mode virtual-memory management operations has been added.
\item The Supervisor Binary Interface (SBI) chapter has been removed, so
  that it can be maintained as a separate specification.
\end{itemize}

\newpage

\section*{Preface to Version 1.9.1}

This is version 1.9.1 of the RISC-V privileged architecture
proposal.  Changes from version 1.9 include:

\begin{itemize}
  \parskip 0pt
  \itemsep 1pt
\item Numerous additions and improvements to the commentary sections.
\item Change configuration string proposal to be use a search process
  that supports various formats including Device Tree String and
  flattened Device Tree.
\item Made {\tt misa} optionally writable to support modifying base
  and supported ISA extensions.  CSR address of {\tt misa} changed.
\item Added description of debug mode and debug CSRs.
\item Added a hardware performance monitoring scheme.  Simplified the
  handling of existing hardware counters, removing privileged versions
  of the counters and the corresponding delta registers.
\item Fixed description of SPIE in presence of user-level interrupts.
\end{itemize}
